First 18 Months: A Tapeout Roadmap You Can Fund

Almost every CMOS image sensor plan we are asked to rescue has the same defect: it treats silicon as a single line item on a Gantt chart. Investors do not fund a chip. They fund a sequence of de-risking events, each one cheap enough to survive if it fails. The plan below is the sequence that gets funded, compressed into eighteen months from incorporation to a first design win.

Months 1–3 — Pick the segment and the node, in that order

The node follows the application, never the other way round. A surveillance sensor chasing cost per megapixel belongs on a 65nm or 90nm CIS process. A scientific or medical sensor chasing read noise and full-well capacity belongs on 180nm, where the larger pixel and thicker epitaxial layer earn their keep. An automotive global-shutter part chasing LED flicker mitigation and a wide dynamic range belongs on a 110nm or 65nm stacked flow. Founders who write "we will use an advanced node" have told the reader they have not spoken to a foundry yet. Spend this quarter defining the pixel pitch, the target quantum efficiency curve, the frame rate, the interface (MIPI CSI-2 is the default), and the one customer requirement your part meets that Sony's catalogue part does not.

Incorporate properly now, too. If the entity is British, the ownership structure you set up in month two is the structure the Investment Security Unit will read in month fourteen, and retrofitting it is far more expensive than getting it right while the cap table still has three lines on it.

Months 3–6 — Process selection, PDK access and a signed NDA with a foundry

Process design kit access is the first real gate. You cannot start layout without the PDK, and the PDK does not arrive until the foundry or its shuttle broker has an NDA and, usually, a purchase commitment for a shuttle slot. Budget six to ten weeks for this alone. In parallel, secure EDA seats. Cadence, Synopsys and Siemens EDA all run startup programmes with discounted first-year pricing; the discount is real, but so is the cliff in year two, and your financial model must show the step-up rather than a flat line across five years.

Months 6–11 — First MPW shuttle: prove the pixel, nothing else

The first run is a pixel test chip, not a product. Put four or five pixel variants on the reticle, a small array of each, a minimal readout chain, and nothing you do not need to measure. Multi-project wafer runs are widely available in the $5,000 to $50,000 band, which makes prototype iteration feasible even for a seed-funded team, according to the Silicon Analysts foundry engagement guide, 2026. Europractice, which brokers X-FAB and TSMC shuttles into Europe, applies a minimum charge of 1.25mm² including seal ring and publishes both a discounted academic rate and a standard commercial rate on its 2026 schedules and prices page. That minimum matters: a pixel test chip that could have been 0.8mm² still costs you 1.25mm², so fill the space with variants rather than paying for empty silicon.

Silicon comes back roughly twelve to sixteen weeks after tapeout. Reserve six weeks after that for characterisation: dark current versus temperature, conversion gain, read noise, quantum efficiency across the visible band, and full-well capacity. Those five numbers are the entire technical section of your seed deck, and no amount of narrative substitutes for them.

Months 11–15 — Second shuttle: the product candidate

Iteration two carries the winning pixel scaled into a real array with the full readout chain, the ADC bank, the MIPI interface and the register map. This is the part you put in front of a customer. Expect a second shuttle slot at the same order of cost as the first, plus colour filter array and microlens processing, which is a separate NRE line and is where first-time budgets quietly blow up.

Months 15–18 — Evaluation kits, one design win, then talk about masks

Build twenty to fifty evaluation boards, get them into the hands of camera-module houses and system integrators, and convert one into a paid NRE agreement or a letter of intent carrying volume. Only then does a full-mask tapeout become a rational commitment. Doing it in the other order — masks first, customers later — is how a $2M seed becomes a $500,000 mask set with nobody to sell to.

Our bespoke business plan service builds this eighteen-month sequence into the milestone schedule and ties each tranche of the raise to the gate that precedes it, which is the structure semiconductor investors expect to see.

What It Actually Costs to Get to Silicon

There is no single startup cost for a CMOS image sensor business because there is no single business. The number is bimodal. If you are integrating somebody else's sensor die into a camera module or a finished vision system, you are looking at $250,000 to $1.5 million (£200,000 to £1.2 million) — a real business with real customers and no mask set. If you are designing your own sensor and taking it to production on a mature node, the honest all-in figure is $2 million to $15 million (£1.6 million to £12 million).

Founders consistently understate the second number. First-time tapeout budgets are routinely underestimated by two to three times because teams focus on wafer cost while overlooking NRE, IP licensing, EDA tools and advanced packaging, per Silicon Analysts' tapeout cost guide, 2026. Wafers are the cheap part. Everything wrapped around the wafer is not.

Silicon access: the numbers to put in your model

• MPW shuttle slot, 65nm, ~4mm² die: $5,000–$15,000 per run (£4K–£12K)
• MPW shuttle slot, 28nm: $20,000–$50,000 per run (£16K–£40K)
• MPW shuttle slot, 7nm: $100,000+ per run (£80K+) — and almost certainly the wrong node for a sensor
• Full-mask tapeout, 180nm: from roughly $500,000 (£400K)
• Full-mask tapeout, 3nm: $100M+ — quoted only to show you the shape of the curve
• Complete first product programme, 28–65nm: $2M–$15M (£1.6M–£12M) including NRE, masks, IP and packaging

Mature nodes are not a compromise for an image sensor; they are frequently the correct engineering answer, because pixel performance depends on photodiode volume and process cleanliness rather than on transistor density. That is a genuine advantage over other silicon startups: your $2M to $15M mature-node entry point is the same range that gets an IoT or edge-AI chip company funded, and you get better physics for the money. Say this explicitly in the plan. A generalist investor will assume "chip company" means "$100M" unless you correct them on page two.

Everything that is not silicon

• Design team (4–6 engineers, year 1): $700,000–$1,300,000 (£380K–£750K) — mixed-signal and pixel-device specialists are the scarcest hire in the stack
• EDA seats (Cadence, Synopsys, Siemens EDA): $30,000–$250,000/yr (£25K–£200K) depending on startup-programme status
• Third-party IP (ADC, PLL, MIPI CSI-2 PHY, SerDes): $60,000–$400,000 in licence fees plus a per-unit royalty
• Colour filter array, microlens and packaging NRE: $150,000–$600,000 (£120K–£480K)
• Optical characterisation lab (integrating sphere, monochromator, probe station, dark box): $120,000–$400,000 (£95K–£320K)
• ATE test programme development: $80,000–$250,000 — a cost that appears in almost no first-draft plan we read
• Export classification and compliance counsel: $15,000–$60,000 (£12K–£45K)
• 12 months working capital (fabless): $400,000–$2,000,000 (£320K–£1.6M)

Funding routes that actually work for this niche

In the US, SBA 7(a) loans are the standard small-business route, and the SBA doubled the cumulative 7(a) and 504 borrowing limit to $10 million in May 2026. Your business sits under NAICS 334413, Semiconductor and Related Device Manufacturing, which carries a 1,250-employee size standard, so eligibility is rarely the obstacle. The obstacle is collateral. The average 7(a) loan in FY2024 was approximately $479,000, with around 30% of loans under $150,000, and manufacturing approval rates sit in the 70–76% band precisely because the sector offers tangible equipment collateral and business-to-business revenue (Crestmont Capital, 2026; SBA 7(a) programme). Read that carefully and the strategy writes itself: a 7(a) facility will finance your probe station, your test floor and your evaluation-kit inventory. It will not finance a mask set, because a mask set has no resale value the day after it is written. Split the raise accordingly — debt against assets, equity against masks.

In the UK, the Start Up Loans scheme offers up to £25,000 per director at 6% fixed with free mentoring. That is meaningful for a module-integration business and close to irrelevant for a design house; say so in the plan rather than padding the funding section with a programme that covers one per cent of your need. The serious UK and European money is institutional or programmatic. The European Chips Act is supported by €6.2 billion of public funds, of which €3.3 billion comes from the EU budget for the period to 2027, backing pilot production lines, a cloud-based design platform, competence centres and a Chips Fund providing access to debt financing and equity. The Chips Joint Undertaking supports five pilot lines with €3.7 billion of European and national funding, and as of October 2025 the Commission reported the Act had catalysed €69 billion across R&D projects and facility investment in Europe. Design-platform and competence-centre access is worth more to a six-person team than a grant cheque, because it substitutes directly for the EDA and PDK costs that dominate year one.

Venture capital in this niche is patient but specific. Prophesee, the French event-based vision company founded in 2014, raised $19 million in the first tranche of its Series B with backing from Intel Capital, Robert Bosch Venture Capital, Renault Group, 360 Capital Partners, Supernova Invest and iBionext, then closed a €50 million Series C in October 2022 with Prosperity7, taking its total raised to $127 million (Imaging and Machine Vision Europe). Look at the composition of that cap table: two automotive strategics and a semiconductor strategic. In image sensors, the strategic investor and the first customer are usually the same organisation, and a plan that does not name the strategics it is targeting is missing its most important page.

Foundries, Shuttle Brokers & the Toolchain You Will Name in the Plan

An operations section that says "we will engage a foundry partner" is a red flag to anyone who has financed silicon. Name the counterparties. Here is the supplier map a CMOS image sensor plan should reference, and what each one is for.

Silicon and shuttle access

• X-FAB — the specialist route for CIS and mixed-signal work on mature nodes; publishes an MPW run schedule through Europractice each year, with the 2026 schedule issued in December 2025
• TSMC CyberShuttle — TSMC's own multi-project wafer programme; the natural path if your product later scales into a full-mask flow at the same foundry
• Europractice — the European broker for X-FAB and TSMC shuttles; two published price tiers (discounted for eligible academic and publicly funded research, standard for everyone else) and a 1.25mm² minimum charge including seal ring
• Muse Semiconductor — US-facing shared-block TSMC MPW access with published pricing, useful when you want a slot without an institutional membership
• CMP (Circuits Multi-Projets) — the long-standing Grenoble-based shuttle service; a second quote to keep the first one honest
• AnySilicon MPW schedule — aggregates foundry shuttle dates across vendors; the cheapest way to align your tapeout milestone with a real calendar rather than an invented one

Design and verification toolchain

• Cadence Virtuoso — analogue and custom layout; where the pixel and the readout chain are actually drawn
• Synopsys Sentaurus TCAD — device-level simulation of the photodiode, well doping and charge transfer, which is the difference between a pixel that works and a pixel that leaks
• Siemens EDA Calibre — DRC, LVS and sign-off; the foundry will name the deck and the version, and you do not get to choose
• Ansys — optical and multiphysics simulation for the microlens stack and crosstalk modelling
• MIPI CSI-2 PHY IP — licensed rather than built; budget the licence and the royalty as separate lines

Where you sell, and who you sell to

• LUCID Vision Labs and Teledyne e2v — machine-vision camera builders who buy sensor die and publish detailed sensor selection criteria; a natural first design-win target
• Camera-module houses — the volume channel for automotive and security parts, and the reason your plan needs a camera module cost model as well as a die model
• Distributors and catalogue channels — low volume, high margin, useful for scientific and industrial parts where a design win is a single instrument line
• Direct to system OEMs — the highest margin and the longest sales cycle; realistic only once you have reference silicon in hand

Supplier and customer names are listed as reference points for your own diligence. Avvale has no commercial relationship with any of them, and none of them endorse this template.

Export Control & Legal Requirements

This is the section that separates a fundable image sensor plan from a hobbyist one. Image sensors are dual-use hardware. The same silicon that fills a doorbell camera fills a targeting system, and the regulators who write the rules know it. Get the classification wrong and the penalty is not theoretical: BIS accepted a $301,000 settlement from an exporter over unlicensed exports of thermal imaging cameras.

United States

• Classify against ECCN 6A002 and 6A003 — 6A002 covers optical sensors and focal plane arrays; 6A003 covers imaging cameras and systems. Control reasons on 6A003.b.4 (thermal imaging cameras incorporating certain focal plane arrays) include National Security, Nuclear Non-Proliferation, Regional Stability and Anti-Terrorism (EAR Part 742, BIS)
• Understand the military end-user trigger — a licence is required for export or re-export to any destination other than Canada for cameras controlled by certain parts of 6A003 where the exporter knows or is informed the item is intended for a military end user or for incorporation into a military commodity. Conversely, BIS no longer requires a licence for items under 6A002 and 6A003 (other than 6A003.a.3, 6A003.a.4 and 6A003.a.6) intended for a military end user in Country Group A:1 countries (Federal Register, February 2024)
• Check ECCN 6A293 — BIS added this classification as a temporary control covering certain cameras not already caught by 6A003 or 6A203, while it seeks multilateral agreement (Nixon Peabody, March 2024)
• Request a CCATS ruling — no filing fee, but budget four to twelve weeks and $15,000–$60,000 in outside counsel to build the classification file
• Open a SNAP-R account before you need it; licence decisions run 30–90 days and your first export order will not wait
• Deemed export — releasing controlled technology to a foreign national employee inside your own US office can itself require a licence. This bites startups with international engineering teams almost immediately, and it is a hiring-plan problem, not a legal footnote

United Kingdom

• National Security and Investment Act 2021 — mandatory notification. The semiconductor sector definition covers "the accessibility of design and production for semiconductor devices and chips", and expressly names Readout Integrated Circuits among the chips in scope. A CMOS image sensor is a photodiode array plus a readout circuit; there is no plausible reading under which a UK sensor design house sits outside this schedule (GOV.UK notifiable acquisitions guidance)
• The thresholds are equity thresholds, not revenue thresholds. Notification is required when an acquisition crosses 25%, 50% or 75% of shares or voting rights in a qualifying entity, or where the acquirer gains the right to pass or block any class of resolution governing its affairs. A seed round that hands an investor 26% is notifiable at pre-revenue, with no product and no customers
• Completing without clearance makes the transaction legally void — this is the detail that costs founders their round. Build the review window into the closing timetable and tell your investors on day one (National Security and Investment Act 2021)
• Strategic export licences via SPIRE — SIEL or OIEL applications to the Export Control Joint Unit at the Department for Business and Trade; no fee, with a 20-working-day target for a standard individual licence
• Watch the sector redefinition. Government has proposed carving semiconductors out of the existing Advanced Materials schedule and merging it with Computing Hardware into a single, more coherent schedule that newly captures advanced packaging techniques, the wider design process for processing units and memory chips, semiconductor-related devices and detectors, and advanced chip designs. If your plan is being read in diligence, cite the current schedule and note the proposal

Third jurisdiction — China and the raw-material chokepoint

• MOFCOM gallium and germanium export controls have applied since 1 August 2023, requiring exporters to hold a licence for dual-use items and technologies with potential military and civilian applications
• Announcement No. 46 of 2024 banned exports of germanium and gallium to the United States; MOFCOM then suspended Article 2 of that announcement from 9 November 2025 until 27 November 2026, so the restriction is paused rather than repealed (Pillsbury, 2025)
• China produced an estimated 900,000 kg of primary gallium in 2025 and dominates germanium refining. If any part of your stack touches compound semiconductors or germanium-sensitive layers for SWIR performance, that November 2026 date is a risk line in your plan, not a footnote
• Practical response: state a qualified second source, or state explicitly that your process uses silicon photodiodes only and therefore sits outside the exposure. Either answer is fine. Silence is not

Our research and content service produces the classification narrative and the jurisdictional risk table as part of the plan. In our experience that is the section founders defer until an investor raises it in week three of diligence, by which point the answer has to be improvised.

Unit Economics: ASP, Yield & the Die Maths Investors Check First

Most plans in this category model revenue as units multiplied by price. Semiconductor investors do not read that line; they go straight to die per wafer, yield and average selling price, and if those three numbers are absent the rest of the model is treated as decoration. Here is what the sheet needs to contain.

What sensor die actually sell for

• Smartphone main and auxiliary sensors: $2–$25 per die — a volume game owned by Sony and Samsung; a startup enters here only with a genuinely novel modality
• Automotive ADAS and viewing sensors: $6–$18 per die, with long qualification cycles and AEC-Q100 obligations attached
• Security and surveillance: $3–$9 per die, brutally cost-driven, very high volume
• Industrial and machine-vision global shutter: $18–$70 per die — the segment where a small team can genuinely win, because the volumes are too low to interest the top five and the performance bar is specific rather than general
• Scientific and medical: $150–$900 per die; tiny volumes, long design cycles, exceptional margins
• IP licensing: $80,000–$500,000 per licence plus a 1–4% royalty, for teams whose pixel or readout architecture is the asset rather than the chip

A worked example: 2.2MP automotive global-shutter sensor

Take a fabless design house shipping a 2.2-megapixel global-shutter part on a 110nm CIS process. The die is 24mm². On a 300mm wafer that yields roughly 2,600 gross die; at 78% yield, about 2,030 good die per wafer. Wafer cost is $3,100. Add $0.42 per die for colour filter array, microlens and packaging and the landed cost of goods is approximately $1.95 per die.

Sell that die to a Tier 1 module house at $7.40 and you make $5.45 of gross profit per die — a 74% gross margin at the die level. Ship 40,000 units per month and the programme grosses $3.55 million of revenue and $2.62 million of gross profit per year.

Now subtract the things founders leave out. A $1.4 million design team. $210,000 of EDA seats. $480,000 of amortised mask NRE. $150,000 of test. The programme nets roughly $380,000 in its first full production year. That is a 74% die-level gross margin collapsing to a 10.7% net margin, and it is the honest picture. It is also why fabless gross margins of 38–55% and net margins of 5–18% are the realistic planning band once a portfolio of parts is running, and why investors underwrite the second and third design win rather than the first. The first one pays for the tooling. The second one is the business.

The break-even number that decides your structure

Run the same maths backwards. A $500,000 full-mask tapeout at 180nm, recovered at $5.45 of gross profit per die, needs roughly 92,000 units to break even on the mask alone — before a single salary is paid. If your addressable segment cannot absorb 92,000 units within the mask's commercial life, a full-mask tapeout is the wrong instrument, and the plan should say so out loud. MPW production, an NRE-funded customer programme, or a licensing model are the financeable alternatives. Stating that choice deliberately reads as competence. Discovering it in year three reads as something else.

Secondary revenue lines worth modelling

Non-recurring engineering paid by a customer to tune a part for their optical stack typically runs $150,000 to $700,000 per programme, and it is the single most under-used revenue line in early image sensor businesses — it converts your R&D cost centre into a funded activity and it validates demand in a way no letter of intent does. Evaluation kits sell at $900 to $4,500 each and, more importantly, qualify the pipeline: a customer who pays for a kit is a customer who has budget. Characterisation as a service, where you rent your optical bench and your expertise to neighbouring startups, will not build a company but has kept several alive between rounds. Model all three. They are the difference between an eighteen-month runway and a twenty-six-month one, and twenty-six months is roughly what two shuttle iterations plus a design win actually take.

The CMOS Image Sensor Market in 2026

The global CMOS image sensor market was valued at $24.32 billion in 2025 and is projected to grow from $26.58 billion in 2026 to $54.29 billion by 2034, a 9.34% CAGR, according to Fortune Business Insights, 2026. Mordor Intelligence puts 2025 at $24.53 billion reaching $36.96 billion by 2031 at 6.99%, while Grand View Research estimated $30.67 billion in 2024 growing to $49.12 billion by 2030 at 7.7%. The spread reflects scope definitions rather than disagreement about direction, and a plan that quotes one figure without acknowledging the range invites a diligence question it does not need to invite. Quote the band. Then state which scope your addressable market uses, and why.

Concentration is the fact that should shape your strategy. Sony Semiconductor Solutions held a 43.4% share in 2025 and Samsung held 20.2%; Sony, Samsung, OMNIVISION, STMicroelectronics and onsemi together held 83.1% (Fortune Business Insights, 2026). OMNIVISION sits at roughly 11%. Asia Pacific accounted for 43.94% of the market in 2025. An eighty-three per cent top-five share means the honest competitive section of your plan is not "how we beat Sony" — it is "which requirement is too small, too specialised or too awkward for a 43%-share incumbent to chase". That is a shorter list than founders fear and a longer one than incumbents admit.

Where the growth is actually coming from

Three demand engines, in order of durability. Automotive is the first: a modern vehicle carries eight to sixteen camera units, and unlike smartphones the count is still rising rather than saturating. Security and surveillance is the second, pulled by 4K resolution and on-device AI recognition, which raises both the pixel count and the readout bandwidth per unit sold — note that this is a bandwidth story as much as a resolution story, and bandwidth is where sensor architecture earns its margin. Industrial and medical imaging is the third and the most hospitable to newcomers, because each design win is a specific instrument with a specific optical requirement, and no incumbent bothers to chase a 30,000-unit programme.

The technology curve, in one paragraph

Front-side-illuminated sensors send light through the metal interconnect before it reaches the photodiode, losing some of it on the way. Back-side illumination flips the wafer so light reaches the photodiode without obstruction from the dielectric and interconnect layers, raising the number of photons converted into electrons and improving low-light response. Stacked construction then bonds a logic wafer beneath the pixel wafer, separating light capture from data processing — and that separation, rather than any improvement in image quality, is what made high-frame-rate video, full-resolution global shutter and on-sensor AI inference possible at all. Sony demonstrated a stacked BSI sensor with a pixel-parallel analogue-to-digital converter to enable global shutter, and the Sony A9 III reads every line simultaneously, removing rolling shutter entirely. Your plan should state where on this curve your part sits and, more importantly, why the incumbents' position on the curve leaves your segment underserved.

There is a genuinely open frontier here too. Event-based vision — Prophesee's territory — reports processing equivalent to up to 100,000 frames per second, dynamic range beyond 120dB, and operation under 10mW, by transmitting only the pixels that change. That is not a better conventional sensor; it is a different contract with the downstream processor, and it is exactly the sort of position a small team can defend. If you are writing a plan for a conventional Bayer sensor at a conventional price, be honest with yourself about which slice of the 83.1% you are asking a customer to switch away from, and what they get for the switching cost.

Related reading: our image sensor semiconductor business plan template covers the broader device category, and the free business plan template hub lists every sector we cover.

Questions Founders Keep Asking

Why is CMOS cheaper to manufacture than CCD?

Because CMOS sensors are built on the same equipment that already makes every other chip. Existing semiconductor manufacturing lines can be repurposed for them, whereas CCD production needs specialised high-voltage analogue processing. CMOS also uses smaller digital circuitry and draws less power. For a startup, the commercial consequence is more interesting than the technical one: because CMOS rides standard CMOS lines, shuttle access exists, PDKs exist, and a six-person team can buy a few square millimetres of a shared reticle. That path does not exist for CCD, which is a large part of why CCD is a legacy category and CMOS is a $24 billion one.

What is a global shutter and why does it justify a price premium?

A rolling shutter reads the array line by line, so anything moving quickly is captured at slightly different instants across the frame and appears skewed. A global shutter captures every pixel at the same moment. In a stacked design, the top layer holds the photosensitive pixels and the layer beneath holds an ADC for each pixel, which allows all pixel data to be read at once rather than in a sequence of lines. For machine vision inspecting parts on a moving line, for drones, for barcode scanning and for anything with a rotating component, rolling shutter is not a quality compromise, it is a functional failure. That is why global-shutter industrial parts sit at $18–$70 per die while rolling-shutter surveillance parts sit at $3–$9, and why the industrial segment is the most rational entry point for a new design house.

How long does an automotive design win take?

Plan for 24 to 36 months from first sample to production revenue, and build the model so the company survives it. AEC-Q100 qualification, functional safety documentation and the Tier 1's own validation cycle each consume quarters, and none of them compress because you ask nicely. Automotive is the most attractive volume in the market and the least forgiving cash-flow profile in it. Founders who put automotive revenue in year two of a five-year forecast lose credibility with the one investor who has done this before — and that is usually the investor whose cheque you actually need.

Should the plan target sensor die, modules, or complete cameras?

Whichever one you can staff. Die is the highest gross margin, the highest capital requirement and the longest path to first revenue. Modules put you in a 12–22% gross margin business with cash arriving inside a year. Complete cameras give you the customer relationship and the pricing power but require software, support and a channel. A defensible plan picks one, states the other two as later phases, and shows the profit and loss for the chosen one only. The plans that fail are the ones promising all three from a £2 million seed.

What kills most CMOS image sensor startups?

In our experience across semiconductor and hardware plans, five things, in this order. Budgeting the wafer and forgetting NRE, IP, EDA and packaging — the two-to-three-times underestimate is close to a law. Committing to a full-mask tapeout before an MPW iteration has proven the pixel. Deferring export classification until the first international purchase order arrives. Writing a competitive section that attacks Sony's 43.4% instead of finding the gap beside it. And, for UK entities, structuring a round without regard to the NSI Act and discovering at completion that the transaction is void. Every one of those is cheap to avoid in the plan and expensive to fix in the company.

Sample Business Plan Preview

Here's an extract from a CMOS image sensor business plan written by our team — so you can see exactly what you'll get:

What's in the Template

Every Avvale business plan template includes these sections, pre-structured for your industry:

• Executive Summary — Your business at a glance, written to hook investors in 60 seconds
• Company Overview — Legal structure, ownership, location, and founding story
• Industry Analysis — Market size, growth trends, and the regulatory picture
• Customer Analysis — Target demographics, pain points, and spending patterns
• Competitor Analysis — Competitive mapping and your differentiation strategy
• Marketing Plan — Channels, messaging, and customer acquisition strategy
• Operations Plan — Day-to-day workflows, staffing structure, and key milestones
• Management Team — Founder bios, advisory board, and key hires planned

For this niche we prompt you through the four extras a generic template will never ask for: the foundry and node decision with a named shuttle route, the die-per-wafer and yield block feeding the revenue model, the export classification position against ECCN 6A002 and 6A003, and the milestone gate that separates MPW iterations from mask commitment. If you have written a plan before and it did not contain those four things, it was a business plan with a chip in it rather than a semiconductor plan.

The optional Financial Forecast add-on (included in our $300/£250 and $1,000/£800 packages) provides a 5-year Excel model with income statement, cash flow, balance sheet, break-even analysis, and startup capital requirements. If you would rather hand the whole thing over, our business plan writers take it end to end.

Frequently Asked Questions