Gnss Chip Business Plan Template

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Gnss Chip Business Plan Template

A founder-grade plan for a fabless GNSS chip company — market data, the real cost of first silicon, export rules and funding. Download the free template or have our consultants write it with you.

$500K–$8M (£400K–£6.3M) Seed to First Silicon
34–45% Typical Fabless Gross Margin
$8.4B (£6.6B, 2025) GNSS Chip Market
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The GNSS Chip Market in 2026

A GNSS chip is the silicon that turns faint signals from Global Navigation Satellite Systems — GPS, Galileo, GLONASS, BeiDou and regional systems like QZSS and NavIC — into a position, velocity and time solution. Every smartphone, drone, tractor guidance system, e-scooter, asset tracker and autonomous platform depends on one. That ubiquity is why the category is large and still growing while many semiconductor niches have flattened.

Estimates cluster in a tight band. Mordor Intelligence (2026) puts the market at $8.84 billion in 2026, growing to $11.58 billion by 2031 at a 5.56% CAGR. SNS Insider (2025) sizes it at $8.40 billion in 2025 and projects $18.80 billion by 2035 at 8.39%, while The Insight Partners (2025) forecasts $9.17 billion by 2031 at 8.3%. The gap between the numbers comes from where each firm draws the line between the bare chip, the module and the correction service — a distinction that matters enormously to your own revenue model, and one this template forces you to make explicit.

Global Market (2025)
$8.4B
£6.6B · 5.6–8.4% CAGR depending on source
Projected by 2031–2035
$11.6–18.8B
Mordor 2031 · SNS Insider 2035
Fabless Gross Margin
34–45%
u-blox posted 34.6% in 2024
Highest-Value Segment
Dual-band RTK
Centimetre precision · 10–40x consumer ASP

Who already owns the shelf space

The market is moderately concentrated, and — unusually — leadership splits cleanly by application, which is where a new entrant finds room. In the automotive segment, Qualcomm, NXP and Renesas dominate the high-volume design wins. In mass-market consumer electronics, MediaTek and Broadcom lead by shipping hundreds of millions of low-cost single-band parts into phones and wearables. High-precision is the interesting frontier: u-blox and Septentrio hold strong positions with specialised dual-band chipsets, and this is the segment where startups are being funded. Qualcomm's Snapdragon W5+ Gen 2 platform, launched in August 2025, added AI-assisted positioning that the company claims tracks 50% more accurately — a signal that even the incumbents see accuracy, not cost, as the next battleground.

The broader competitor set a business plan must map includes STMicroelectronics (Teseo automotive line), Sony, Samsung, Intel, Infineon, Quectel, Telit Cinterion, Unicore Communications, Furuno, Hemisphere GNSS, Topcon and Trimble. Most stop at listing these names. The number that actually drives a fundable plan is where each competitor is weak: power consumption for battery-powered trackers, time-to-first-fix in dense urban environments, jamming and spoofing resilience, and the price-to-precision ratio for robotics. Those gaps are your wedge, and the plan should name the one you are attacking.

Fabless design as a whole is expanding fast — the segment was worth roughly $214.5 billion in 2024 and is forecast to reach $489 billion by 2034 (Market.us) — which keeps foundry capacity, IP ecosystems and specialist talent flowing toward exactly the kind of company you are proposing to build.

Questions Founders Ask First

These are the questions that surface earliest when someone researches a GNSS chip venture. Getting crisp answers into the plan early tells an investor you understand the terrain.

Do I need my own fab to make GNSS chips?

No, and no positioning-chip startup does. The model is fabless: you own the architecture, RTL and IP, then contract a foundry — TSMC, GlobalFoundries, UMC or SMIC — to fabricate wafers, and an assembly-and-test house such as ASE or Amkor to package them. Your capital goes into design tools, engineering payroll and mask sets, not a fabrication plant. This is the single most important framing in the whole plan, because it changes the capital ask from billions to millions.

What is the difference between a GNSS chip and a GNSS module?

The chip is the bare die or packaged IC that acquires signals and computes a fix. The module wraps that chip with the parts a customer would otherwise have to design themselves — the RF front end, a temperature-compensated oscillator, SAW filters, flash memory and an antenna interface — so a product team with no RF expertise can drop positioning into their device. Modules sell for two to four times the bare-die price. Many founders assume they are a "chip company"; the durable margin is often in the module and the correction subscription that rides on top of it.

Which satellite constellations should the chip support?

A competitive chip in 2026 tracks GPS, Galileo, GLONASS and BeiDou as a baseline, and increasingly adds QZSS and NavIC for regional coverage. More constellations means more visible satellites, which means a faster and more reliable fix in urban canyons and under foliage. If you are targeting the high-precision segment, dual-frequency support (L1 combined with L5 or L2) is the gate to RTK and PPP — the techniques that reach centimetre accuracy and justify a selling price ten to forty times that of a consumer part.

How long until I have production silicon?

Plan for 18 to 36 months. Architecture, RF and digital design plus verification is usually 9 to 15 months; the foundry cycle adds 3 to 5; bring-up, firmware, field testing and a respin absorb the balance. Investors who have funded silicon before will probe this timeline hard, so it needs to be defensible rather than optimistic.

What First Silicon Really Costs

Starting a fabless GNSS chip company typically needs $500,000 to $8 million (£400,000 to £6.3 million) to reach validated first silicon, and materially more — often $10M to $30M — to carry a part through qualification and into volume production. The spread is enormous because two decisions dominate everything else: the process node you choose and whether you prototype on a shared shuttle or commit to your own mask set.

The cost driver almost nobody outside the industry appreciates is the mask set. According to Silicon Analysts, a full-mask tape-out on a mature 28–65nm node runs $2 million to $15 million, while a 180nm mask can start near $500K and an advanced 5nm programme can exceed $300 million. The good news for GNSS: a positioning chip's power and accuracy targets are usually met comfortably on a mature node, so you rarely need to pay advanced-node prices. Better still, a multi-project wafer (MPW) shuttle — where your design shares a wafer with other companies — can put first silicon in your hands for $5,000 to $100,000, per AnySilicon. An MPW-first roadmap is the standard way to de-risk a deep-tech raise.

The fabless cost stack

  • EDA tool licences (Synopsys, Cadence, Siemens EDA): $100K–$500K/yr (£80K–£400K) — the recurring software cost of designing silicon at all
  • IP core licences (Arm Cortex-M, CEVA DSP, RISC-V): $50K–$500K (£40K–£400K), often plus per-unit royalties
  • MPW shuttle prototype (28–65nm first silicon): $5K–$100K (£4K–£80K)
  • Full-mask tape-out (mature node, production): $2M–$15M (£1.6M–£12M)
  • GNSS RF lab + signal simulator: $150K–$600K (£120K–£480K)
  • Engineering payroll (RF, DSP, digital, firmware), 12 months: $800K–$3M (£640K–£2.4M)
  • Certification, export classification & legal: $30K–$120K (£24K–£95K)

A defensible 24-month roadmap

Investors judge a silicon plan by whether its milestones are sequenced credibly and whether each round of capital buys a clear risk reduction. A roadmap that survives scrutiny usually looks like this:

  • Months 0–3: lock the architecture, secure EDA seats and IP licences, and complete the export-control classification so it never becomes a surprise later.
  • Months 3–9: RF and digital design plus verification, with FPGA prototyping of the baseband to catch bugs before any silicon is committed.
  • Months 9–12: MPW shuttle tape-out — first silicon in hand for a five-figure sum rather than a seven-figure mask commitment.
  • Months 12–18: bring-up, firmware, signal-simulation validation and field test; fund the near-inevitable respin here rather than pretending it will not happen.
  • Months 18–24: full-mask production tape-out, qualification, and the first one or two lighthouse design wins that open the next round.

The point of laying the roadmap out this explicitly is that it lets an investor see exactly which milestone their cheque funds — and it forces you to price each stage honestly rather than presenting one undifferentiated lump sum.

Funding routes for a deep-tech chip

GNSS chip companies are rarely funded by bank debt — the risk profile is wrong for a lender, and SBA 7(a) loans in the US were built for cash-flowing small businesses, not multi-year R&D burns. The realistic capital stack is equity plus non-dilutive grants. In the UK, SEIS lets you raise up to £250,000 with 50% income-tax relief for investors, followed by EIS for larger rounds, and Innovate UK Smart Grants regularly back positioning and PNT hardware with £100K–£500K of non-dilutive money. In the US, SBIR/STTR awards from agencies such as the NSF, DoD and NASA are a common first cheque for PNT startups, ahead of a deep-tech seed round. Recent proof that the category is fundable: Qualinx of Delft raised €20 million to scale an ultra-low-power GNSS SoC, and HYFIX Spatial Intelligence closed a $15 million seed led by Craft Ventures for a drone-and-robotics positioning SoC. Our bespoke plan bakes the respin and the grant timeline directly into the model, because that is what separates a credible raise from an optimistic one.

Which Segment You Are Actually Selling Into

"GNSS chip" is not one market — it is at least four, each with a different buyer, price point and competitive set. The plan's most important early decision is which one you are attacking, because it cascades into your node choice, headcount, certification path and funding need. Investors will not fund a company that claims to serve all of them at once.

  • Mass-market consumer: phones, wearables, e-scooters and low-cost trackers. Single-band, sub-$3 parts, hundreds of millions of units, brutal price competition led by MediaTek and Broadcom. Winnable only with a genuine cost or power advantage at scale.
  • Automotive: navigation, telematics and ADAS sensor fusion, dominated by Qualcomm, NXP and Renesas. Long qualification cycles (AEC-Q100, ISO 26262) but sticky, high-volume design wins once you are in.
  • High-precision / RTK: drones, robotics, survey, precision agriculture and machine control. Dual-band chips at $8–$40, led by u-blox and Septentrio. This is where startups are raising money because accuracy, not cost, decides the sale.
  • Timing & synchronisation: a distinct market where the "T" in PNT anchors telecom base stations, data centres and power-grid infrastructure. Lower volume, high value, and less crowded than positioning.

A sharp plan quantifies the target segment's size, the buying criteria that decide a socket, and how messaging shifts between, say, a drone OEM and a survey-equipment maker. It also names the two or three lighthouse customers whose design win would validate the whole thesis — specificity here is what separates a fundable plan from a wish.

Your Fabless Supply Chain & Partners

A GNSS chip business plan lives or dies on its supply-chain credibility. Investors want to see that you know exactly who fabricates, packages, tests and tools your part, and that those relationships are realistic for a company your size. Naming the ecosystem — and showing you understand what each layer costs — is a Tier-one signal of seriousness.

  • Foundries: TSMC, GlobalFoundries, UMC, SMIC and Samsung Foundry fabricate your wafers. GlobalFoundries and Qualinx recently completed what they described as the first fully European end-to-end flow for a GNSS SoC — relevant if supply-chain sovereignty is part of your pitch.
  • EDA vendors: Synopsys, Cadence and Siemens EDA supply the design, simulation and verification tools. Seat count and licence tier drive a recurring six-figure line in your budget.
  • IP core providers: Arm (Cortex-M processors), CEVA (DSP cores for signal processing), and the growing RISC-V ecosystem (e.g. SiFive) license the digital blocks so you focus engineering on the GNSS baseband, not reinventing a CPU.
  • OSAT / packaging & test: ASE, Amkor and JCET handle assembly, packaging and final test — the back end most first-time founders forget to budget.
  • GNSS signal simulators: Spirent (GSS7000-class systems), Safran/Orolia and Rohde & Schwarz reproduce controlled multi-constellation scenarios so you can validate accuracy, time-to-first-fix and jamming resilience without waiting for good sky.
  • FPGA prototyping: AMD (Xilinx) and Altera boards let you validate the digital design before committing to a mask set.

The plan should also address second-sourcing. A single-foundry dependency is a risk an experienced investor will flag immediately; even naming a credible backup foundry and a qualification plan for it strengthens the operations section considerably.

Pricing, Margins & Unit Economics

GNSS silicon spans an extraordinary price range. A commodity single-band consumer chip might sell for $0.50 to $3 at volume, where the whole game is shipping tens of millions of units at razor-thin margin. A high-precision dual-band or RTK-capable chip aimed at drones, survey equipment, robotics or precision agriculture can command $8 to $40, and the module built around it several times that again. Deciding which end of that spectrum you are attacking is the most consequential line in the entire plan, because it dictates your process node, your headcount, your go-to-market and your funding need.

Fabless gross margins in this space run 34–45%. The public benchmark is u-blox: in 2024 the company reported CHF 621.4 million revenue against CHF 406.6 million cost of goods — a 34.6% gross margin — while spending roughly 19% of revenue on R&D. That R&D ratio is the number founders underestimate: a positioning-chip company is a permanent engineering organisation, not a build-once product.

A worked example

Suppose you ship 3 million dual-band positioning chips at a $6 average selling price, with a fully-loaded die cost of $3.30 (wafer, packaging, test and amortised mask). Revenue is $18M; gross profit is about $8.1M at a 45% gross margin. Layer a positioning-correction subscription at $12 per active device per year onto even 100,000 of those devices, and you add $1.2M of high-margin recurring revenue that an investor will value far more richly than the silicon itself. That correction-service attach is the strategic move the incumbents have all made, and the plan should show whether and when you follow them.

Additional revenue lines to model: module sales at a 2–4x markup over the bare die, IP or reference-design licensing to customers who want to integrate your baseband, NRE fees for custom variants, and paid firmware feature tiers. A plan that shows three or four stacked revenue streams reads very differently from one betting on a single per-chip price.

Why gross margin is so sensitive

In fabless economics, the cost of goods is dominated by wafer price, packaging, test and the amortised mask set — and that amortisation is where volume changes everything. A $10 million mask-and-development spend spread across 500,000 units adds $20 to every chip; the same spend across 5 million units adds only $2. This is why GNSS chip plans are so unforgiving of weak volume assumptions: the difference between a design that scales and one that stalls is not the engineering, it is whether you win enough sockets to amortise the fixed cost. The financial model should therefore run at least three volume scenarios and show the gross margin at each, so an investor can see the point at which the business becomes structurally profitable rather than being asked to take it on faith. A single optimistic volume line is the fastest way to lose a technical investor's confidence.

Where GNSS Chip Companies Cluster

Location shapes access to RF and DSP talent, foundry relationships and specialist investors. A GNSS chip venture does not need to be in Silicon Valley, but it does need to be somewhere the ecosystem exists. The plan's team-and-location section should be honest about which cluster you are drawing talent from.

  • San Diego, USA: Qualcomm's home turf and the deepest pool of GNSS and cellular-positioning engineers in the world; expensive but unmatched for wireless silicon talent.
  • Cambridge & Bristol, UK: a dense semiconductor-IP and RF cluster (Arm's ecosystem, Cambridge Consultants, Dialog/Renesas alumni) with access to SEIS/EIS angels and Innovate UK grants.
  • Delft & Eindhoven, Netherlands: home to Qualinx and a strong low-power RF design community around TU Delft and the wider Brainport ecosystem.
  • Hsinchu, Taiwan: immediate proximity to TSMC and UMC, shortening foundry engagement and cutting travel out of the design-iteration loop.
  • Shenzhen, China: the module and integration heartland — relevant if BeiDou, cost leadership and rapid hardware iteration are central to your strategy.
  • Bengaluru, India: a fast-growing chip-design talent base with NavIC as a home-market anchor and strong government backing for domestic semiconductor design.

Investors read the location choice as a proxy for how quickly you can hire the RF architect and the DSP lead who make or break first silicon. If you are outside a cluster, the plan should explain how you will attract those two or three critical hires anyway.

Export Control, Certification & Compliance

Positioning silicon sits inside a web of radio and export regulation that a generic business plan will miss entirely — and that a customer's compliance team will ask about before they design you in. Getting the classification right early is both a risk-management and a sales-enablement move.

United States

  • A pure GNSS receiver generally does not need an FCC equipment authorisation, but any product with RF emissions must meet FCC Part 15 limits for unintentional radiators (test typically $3K–$15K, 4–8 weeks).
  • Export classification usually lands at ECCN 7A994 for receiver modules, while GNSS antennas commonly fall under EAR99, per the U.S. Department of Commerce (BIS).
  • A receiver only crosses into stricter ITAR / U.S. Munitions List Category XV control if it is designed to compute a navigation solution above 60,000 feet and 1,000 knots simultaneously — the long-standing COCOM missile-technology threshold, summarised by the Office of Space Commerce. The vast majority of civil and commercial parts stay under the EAR.

United Kingdom

  • UKCA marking and the Radio Equipment Regulations 2017 apply to any module with an RF interface, enforced by the Office for Product Safety and Standards (test £3K–£20K, 6–12 weeks).
  • Dual-use export licensing runs through the Export Control Joint Unit (ECJU) via the SPIRE system; a standard individual export licence typically takes 20–40 working days.
  • Products must also meet RoHS and REACH substance rules to be sold in the UK market.

European Union (and beyond)

  • CE marking under the Radio Equipment Directive 2014/53/EU is mandatory for RF-bearing modules sold in the EU.
  • Exports are governed by the EU Dual-Use Regulation 2021/821, which mirrors much of the US classification logic for GNSS receivers.
  • Other markets add their own gates — India's WPC and BIS registration, Japan's MIC/TELEC certification — that a plan targeting global distribution should acknowledge.

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GNSS Terms Your Investors Will Test You On

Deep-tech investors probe vocabulary to gauge whether a founder actually understands the technology. These are the terms that come up in the room — define them correctly in the plan and you signal command of the field.

  • GNSS: Global Navigation Satellite System — the umbrella term covering GPS, Galileo, GLONASS, BeiDou, QZSS and NavIC together, rather than any single constellation.
  • PNT: Positioning, Navigation and Timing — the three outputs a GNSS chip delivers; the "timing" leg alone underpins telecom and power-grid synchronisation and is a distinct market.
  • SoC: System-on-Chip — integrating the GNSS baseband, a processor and often connectivity onto one die to cut cost, size and power.
  • TTFF: Time-To-First-Fix — how long the chip takes to report a position from cold start; a headline spec buyers compare directly.
  • RTK: Real-Time Kinematic — a technique using carrier-phase data and a reference station to reach centimetre accuracy; the basis of the high-value segment.
  • PPP: Precise Point Positioning — reaching high accuracy using correction data without a local base station, often sold as a subscription.
  • Multipath: signal reflections off buildings and terrain that corrupt the position solution; suppressing it well is a genuine competitive advantage.
  • Tape-out: the moment the finished chip design is sent to the foundry to make masks — the point of no return where most of the cash is committed.

Five Mistakes That Sink GNSS Chip Startups

Deep-tech investors have seen positioning-chip pitches fail for the same handful of reasons. Pre-empting them in the plan is one of the cheapest ways to build credibility.

1. Chasing a bleeding-edge process node

Founders sometimes assume they need the newest node to look serious. In GNSS they almost never do — 40nm to 65nm meets the power and accuracy envelope of most positioning parts, and a mature-node mask set costs a fraction of an advanced one. Paying for 5nm when 40nm would do can burn the entire seed round before first silicon.

2. Budgeting a single tape-out

The most common financial error is modelling one trip to the foundry. Almost every first-time GNSS chip needs at least one metal or full respin to fix a bug found in bring-up. A plan that funds only one tape-out is a plan that runs out of money at the worst possible moment; a plan that funds the respin explicitly reads as written by someone who has done it before.

3. Treating export control as an afterthought

Classification (ECCN, EAR99, the ITAR threshold) is not paperwork you handle after launch — it is a gate your first serious customer's compliance team opens before they design you in. Founders who leave it until a shipment is blocked lose months and, sometimes, the account.

4. Positioning as a pure chip vendor

The bare die is the lowest-margin point in the value chain. The companies that win — u-blox being the clearest example — capture margin in the module and, increasingly, in a recurring correction service. A plan that ignores the module and subscription layers is leaving both margin and enterprise value on the table.

5. Under-resourcing signal simulation and field test

Time-to-first-fix, multipath rejection and jamming resilience are what buyers actually compare, and you cannot validate them by waiting for clear sky. Skimping on a Spirent-class simulator and a disciplined field-test programme is how a technically sound design ships poor real-world numbers and loses the design win.

Turning the wedge into design wins

In silicon, revenue does not begin with a sale — it begins with a design win, the moment a customer commits your part into their product. Design-win cycles in automotive and industrial can run 12 to 24 months, which is why the plan must show a realistic pipeline of lighthouse customers, the specific sockets you are targeting, and how the company survives the long gap between tape-out and first volume revenue. Investors fund the bridge across that gap; the plan has to make the bridge visible.

Sample Business Plan Preview

Here is an extract from a GNSS chip business plan written by our team — so you can see the level of specificity investors in deep-tech hardware expect:

Executive Summary — Extract

PulsarNav Semiconductor

PulsarNav Semiconductor is a fabless design company developing a dual-band (L1/L5) low-power GNSS system-on-chip for drones, robotics and high-value asset tracking, where existing consumer chips deliver poor accuracy and precision receivers cost too much and draw too much power. The founding team combines a former u-blox RF architect and a DSP lead from the automotive-positioning sector.

Our roadmap is deliberately MPW-first: the initial design will validate on a 40nm multi-project wafer shuttle for under £80,000 before any full mask set is committed, de-risking the largest single line in the budget. Production silicon is targeted for month 24, with one planned respin explicitly funded. The company is raising a £2.4m pre-seed — £250,000 via SEIS, the balance from EIS-qualifying angels and a secured £400,000 Innovate UK Smart Grant — to reach validated first silicon and two lighthouse design wins. Gross margin is modelled at 42% at a $6 blended ASP, rising as the PPP correction subscription attaches to the installed base from year three...


What's in the Template

Every Avvale business plan template is pre-structured for your industry. For a GNSS chip venture, each section is prompted toward the detail a deep-tech investor expects:

  • Executive Summary — the wedge, the team's silicon pedigree, the capital ask and the milestone it buys, in 60 seconds
  • Company & Technology Overview — architecture, target node, constellation and band support, and what is genuinely differentiated
  • Market Analysis — sized by segment (consumer vs. automotive vs. high-precision) with the CAGR and sources that support your slice
  • Customer & Design-Win Strategy — the lighthouse customers, the sockets you are targeting and the sales cycle to a design win
  • Competitive Analysis — mapped against u-blox, Qualcomm, Broadcom, MediaTek and the specialists, by the axis you win on
  • Operations & Supply Chain — foundry, IP, OSAT, test and second-sourcing, with the tape-out and respin plan
  • Regulatory & Export Plan — ECCN classification, FCC/CE/UKCA path and the dual-use licensing timeline
  • Management & Advisory — the RF, DSP and firmware leads, and the industry advisors who de-risk the raise

The optional Financial Forecast add-on (included in our $300/£250 and $1,000/£800 packages) provides a 5-year Excel model with income statement, cash flow, balance sheet, a tape-out-and-respin capital schedule, break-even analysis and the funding-round structure — the numbers a deep-tech investor will interrogate line by line. You can also compare adjacent programmes with our anti-jamming GPS business plan template, the assured PNT business plan template, and the 5G chipset business plan template.


Deep-Tech Hardware — Client Composite

How an Ex-u-blox Engineer Raised £2.4M for a Dual-Band GNSS SoC

A first-time founder in Cambridge — formerly an RF architect at a positioning-chip maker — came to Avvale with strong silicon credentials but no fundable plan and no financial model. We built a bespoke plan around an MPW-first roadmap that validated the design on a 40nm shuttle before any mask commitment, and a five-year model that funded a respin and the export-classification work explicitly rather than pretending they would not happen. The plan secured a £250,000 SEIS round, a further £1.35M from EIS-qualifying angels, and an £800,000 blend of Innovate UK grant and matched capital — £2.4M in total, enough to reach validated first silicon and two lighthouse design wins in drone and asset-tracking customers.

Composite based on real Avvale client outcomes. Name and identifying details changed for confidentiality.

Read more case studies →
Muhammad Tayyab Shabbir - Founder, Avvale
Muhammad Tayyab Shabbir
Founder & Lead Consultant, Avvale

Tayyab has over 7 years of startup consulting experience and has helped launch 300+ businesses across 30 countries. He co-authored a book that is taught at University College London, where he earned both his undergraduate and postgraduate degrees in Theoretical Physics. He personally reviews every bespoke business plan before delivery.


Frequently Asked Questions

How much does it cost to design a GNSS chip?
A lean, MPW-first programme on a mature node can reach first silicon for roughly $500K to $3M once EDA seats, IP licences and a shuttle run are covered. A full commercial programme with its own mask set and a respin usually lands between $5M and $30M. The single biggest variable is the process node: a 40-65nm mask set costs a fraction of an advanced node, and mature nodes are usually adequate for the power and accuracy a positioning chip needs.
What is the difference between a GNSS chip and a GNSS module?
The chip is the bare silicon die or packaged IC that does the signal acquisition and position solution. The module is a small board that adds the chip's supporting components — RF front end, TCXO, SAW filters, flash and antenna interface — so a customer can integrate positioning without RF design skill. Modules sell for roughly two to four times the bare-die price, which is why many chip vendors capture more margin by selling modules and correction services rather than silicon alone.
Do I need my own fab to make GNSS chips?
No. Almost every GNSS chip company today is fabless: you design the chip and license IP, then a foundry such as TSMC, GlobalFoundries or UMC manufactures the wafers and an OSAT partner like ASE or Amkor packages and tests them. Owning a fab is a multi-billion-dollar undertaking that no positioning-chip startup attempts. Your business plan should model foundry NRE, mask costs and wafer pricing rather than plant construction.
Are GNSS chips export controlled?
Most civil and commercial GNSS receiver chips are controlled under the U.S. Export Administration Regulations, typically ECCN 7A994, while GNSS antennas usually fall under EAR99. A receiver crosses into stricter ITAR / U.S. Munitions List territory only if it is designed to output a navigation solution above 60,000 feet and 1,000 knots at the same time — the classic missile-technology threshold. Classify your part early, because a customer's compliance team will ask for the ECCN before they design you in.
Which satellite constellations should a GNSS chip support?
A modern multi-constellation chip typically tracks GPS (US), Galileo (EU), GLONASS (Russia), BeiDou (China) and regional systems such as QZSS (Japan) and NavIC (India). Supporting more constellations improves availability and accuracy in urban canyons. High-precision designs add a second frequency band (L1 plus L5 or L2) to enable RTK and PPP techniques that reach centimetre-level positioning, which commands a much higher selling price than a single-band consumer chip.
How long does it take to bring a GNSS chip to market?
Expect 18 to 36 months from architecture to production-qualified silicon. Digital and RF design plus verification typically run 9 to 15 months, a foundry tape-out and fabrication cycle adds 3 to 5 months, and bring-up, firmware, field testing and a near-inevitable respin consume the rest. Budgeting for one tape-out is the most common planning error; almost every first-time GNSS chip needs at least one metal or full respin before volume.

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